The present invention relates in general to a semiconductor device and to a method of manufacture thereof; and, more particularly, the invention relates to a technique to be applied to a semiconductor device having a plurality of semiconductor chips and a manufacturing method of manufacture thereof.
Further, the present invention relates to a semiconductor device, and particularly to a technique to be applied to a test on a semiconductor device, such as an SIP (System In Package) or the like, in which a plurality of semiconductor chips are mounted to a single package.
In a conventional multi-chip package (semiconductor device) having a plurality of semiconductor elements (semiconductor chips), some of the leads are extended from one edge of a semiconductor element to the other edge thereof without making contact with a main surface of at least one semiconductor element. Thus, the leads and the semiconductor elements are solid-crossed. Internal electrodes of the plural semiconductor elements are connected to common leads by bonding wires. Reference is made, for example, to Japanese Unexamined Patent Publication No. Hei 6 (1994)-151685 (FIG. 1).
Upon testing of a semiconductor device such as an SIP, there is a need to perform leakage tests on input/output terminals of a plurality semiconductor chips (hereinafter simply called “chips”) that are mounted to the SIP, for example, even on terminals which do not need to be output to the outside of the SIP. Thus, all terminals used for connecting among chips mounted to the SIP have heretofore been extended to the outside of the SIP to ensure easiness or serviceability of such a post-assembly test.
Incidentally, Japanese Unexamined Patent Publication No. Hei 9 (1997)-160802 discloses a means for testing each memory in an SIP containing a CPU and a memory. Further, Japanese Unexamined Patent Publication No. Hei 10 (1998)-123212 discloses a means for detecting a leakage current in a non-contact manner with respect to each input/output terminal.